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작성일 : 18-03-23 14:45
2018년 3월 28일 (수) 콜로퀴움 공지
 글쓴이 : 응용물리학과
조회 : 81  
2018.03.28 (수) 콜로키움 공지입니다.
학부생 분들의 많은 참여 바랍니다.

◎ 강사 : 김우희 교수(전북대 신소재공학과)

◎ 일시 : 2018.03.28(수) 오후 4시 30분~

◎ 장소 : 응용과학대학관 309호 세미나실

Nanoscale Surface Engineering for Advanced Nanoelectronics: Thin Film Process & Engineering in Nanofabrication
  Surface engineering is a sub-discipline of materials science and engineering that deals with the surface of solid matter. Conventionally, from tribological point of view, the surface engineering has received a great deal of attention, especially for wear/friction/corrosion/ fatigue-protection coating technologies in automotive and aerospace industries, pursuing improved hardness and thermal stability with sufficiently good adhesion. Meanwhile, we are already living in a nano-era (i.e. length scale of approximately 1 - 100 nanometer range) that requires nanoscale surface engineering. In the modern nanotechnologies, accordingly, the advanced nano-surface engineering basically aims to provide additional functionality, such as mechanical, electrical, magnetic, and optical characteristics, to the solid surface, not found naturally in the original solid surface. It can be enabled through surface modification/functionalization, where a material surface itself can be transformed or through surface coating technologies, where additional structures and compositions can be added. In this seminar, therefore, we focus on recent trends in the advanced nanoscale surface engineering implemented for modern nanoelectronics. As Si-based technology node nears ~10 nm and approaches its physical limit, alternative surface engineering techniques based on atomic layer deposition (ALD) and atomic layer etching (ALE), are extremely required for further extension of Moore’s law, together with structural challenges of integration-feasible 3D nanostructures such as 3D FinFETs and nanowires (NWs) in place of the conventional planar MOSFET. In addition, extremely fine-feature patterning is also required to satisfy the increasing process complexity of modern electronic devices beyond the sub-10 nm technology regime. Therefore, we further explore nanoscale bottom-up hybrid nanofabrication methods, based on various self-assembled nanopatterning processes using nanotemplates and area-selective ALD.